Method of forming low threshold voltage vertical power transistor using epitaxial technology
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United States of America Patent
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Jun 23, 1998
Issued Date -
N/A
app pub date -
Jul 17, 1997
filing date -
Aug 4, 1992
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Expired
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Abstract
A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.
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