Apparatus and method for generating circuit net list from mask pattern data

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United States of America Patent

PATENT NO 5764530
SERIAL NO

08398680

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Abstract

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A system and method is presented for generating a computer assisted design circuit net list descriptive of a semiconductor integrated circuit design based on mask patterns used during the formation of the semiconductor. Masking pattern data, stored in a library data base, is processed by a central processing unit into primitive elemental circuit data and interconnection data. Coordinate and other information included in the primitive and interconnection data is then simplified. The simplified data is then supplemented to account for data simplification. The supplemented data is further processed to generate a symbolic circuit layout and a primitive net list.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITED1-1 KAMIKODANAKA 4-CHOME NAKAHARA-KU KAWASAKI-SHI KANAGAWA 211-8588

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Yokomaku, Hitoshi Kasugai, JP 2 24

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