Mechanism for maintaining data coherency in a branch history instruction cache
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United States of America Patent
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May 5, 1998
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N/A
app pub date -
Oct 18, 1993
filing date -
Oct 18, 1993
priority date (Note) -
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Abstract
A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target instruction stream is provided from the BTB. The target instruction stream prefetched from cache is then compared with the predicted target stream selected from the BTB. Upon encountering a mismatch, the predicted instruction stream is canceled and the instructions from cache are utilized. Additionally, predicted branch target addresses are stored in a BTB, similar to a branch history table, and circuitry is provided for comparing the predicted target address with an actual target address during processing of the branch instruction. Again upon encountering a mismatch, instruction from cache as addressed by the actual target address are utilized and predicted instructions are canceled. By utilizing the target address comparison along with the target instruction stream comparison a performance gains is made because mismatches can be detected earlier.
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