Data processing apparatus for executing a vector operation under control of a master processor
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United States of America Patent
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Apr 21, 1998
Issued Date -
N/A
app pub date -
Feb 15, 1996
filing date -
Jan 28, 1992
priority date (Note) -
Expired
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Abstract
A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.
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