Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof
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United States of America Patent
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Apr 21, 1998
Grant Date -
N/A
app pub date -
Mar 19, 1993
filing date -
Mar 19, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
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