Flexible IC layout method
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United States of America Patent
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Apr 21, 1998
Grant Date -
N/A
app pub date -
Jun 12, 1995
filing date -
May 13, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is related to a flexible IC layout method utilized for an IC having a plurality of logic gates in a first direction connected with a plurality of logic gates in a second direction wherein each of the logic gates has at least one polysilicon region and each of the logic gates in the first direction has an output serving as an input of a corresponding one of the logic gates in the second direction, which includes a step of forming input terminals for the logic gates by ion implantation. The present invention is flexible because the addition or deduction of the number of the input terminals according to the present invention can be achieved by ion implantation.
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