Controllable precision on-chip delay element
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United States of America Patent
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Mar 24, 1998
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N/A
app pub date -
Sep 13, 1996
filing date -
May 25, 1995
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Abstract
A controllable precision delay line implemented in a digital integrated circuit device including a counter circuit for measuring a representative propagation delay for a delay element in the digital integrated circuit, and a binary controlled digital delay line responsive to the counter circuit and including L delay stages respectively having 2.sup.0 through 2.sup.L-1 delay elements, wherein the delay stages are controllably switched into a delay path pursuant to the measured representative propagation delay. Preload connections are provided between the outputs of delay elements of stages S(0) through S(L-2) and inputs of delay elements of the next in sequence stages S(1) through S(L-1) to prevent glitches being imposed on the delayed signal during adjustments in the number of stages included in the delay path.
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