Focal plane array integrated circuit with individual pixel signal processing
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United States of America Patent
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Mar 17, 1998
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jul 27, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.
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