Envelope detector including sample-and-hold circuit controlled by preceding carrier pulse peak(s)

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United States of America Patent

PATENT NO 5724002
SERIAL NO

08662604

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A sampling synchronous envelope detector adopts a specialized sample-and-hold ('S&H') approach, basing a detected output on instantaneous values of the carrier waveform which are sampled at specially chosen instants. Non-linear distortion is avoided by timing the sampling instants to occur at or near a carrier wave peak which is subsequent to an earlier carrier wave peak which serves as a time base. Sampling instants occur only at or near positive carrier peaks (or only at or near negative peaks) in a half-wave embodiment, and sampling instants occur at or near both positive and negative carrier peaks in a full wave embodiment. Another aspect of the detector provides means, such as a phase locked loop, for ensuring that the phase of the sampling instants is maintained continuously, even in the event of carrier pinch-off or other event which distorts or minimizes the carrier waveform from which the timing instants would otherwise be determined. Still another aspect of the detector provides for low pass filtering, and group delay equalization of the filtered signal, before it is output.

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Patent Owner(s)

Patent OwnerAddress
ACRODYNE INDUSTRIES INC516 TOWNSHIP LINE ROAD BLUE BELL PA 19422

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hulick, Timothy P Schwenksville, PA 9 303

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