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Abstract

A reset pulse generating circuit is disclosed for generating reset pulses that are used for placing digital systems such as microprocessors into a known state upon power-up and when power fluctuations occur. The reset pulse generating circuit includes a memory circuitry and a counter circuitry, and is designed to work in conjunction with a threshold detector circuitry that monitors the level of the power supply voltage and provides a binary output indicating whether the power supply voltage is above or below a threshold value. The memory circuitry includes four series-connected D-type flip flops, the first two of which are resetable in response to fluctuations in the supply voltage and asynchronous to the system clock. The asynchronous reset inputs of the latter flip flops are for coupling to the output of the threshold detector circuitry. The output of the memory circuitry is used to control the counter circuitry. In turn, the counter circuitry provides the reset pulse.

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First Claim