Circuit for testing a semiconductor chip having embedded arrays intermixed with logic
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United States of America Patent
Stats
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Feb 10, 1998
Grant Date -
N/A
app pub date -
Feb 21, 1995
filing date -
Jul 7, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.
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Patent Citation Ranking
- 6 Citation Count
- G01R Class
- 2.99 % this patent is cited more than
- 27 Age