Importance

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Abstract

A resolution conversion system for real-time expansion and reduction of a first plurality of input pixels into a second plurality of output pixels. The resolution conversion system comprises a base-n counter for counting input pixels as each pixel is captured. The base-n counter has a plurality of carry out signals. Also, there is a control register for selectively enabling the carry out signals of the base-n counter based on a predetermined resolution ratio between the first plurality of input pixels and the second plurality of output pixels. The control register uses a mode bit to select either one of inserting and removing operations. An inserting logic unit is used for inserting, as indicated by the mode bit, a pixel into the plurality of input pixels upon a transition of one of the carry out signals if the carry out signals have been enabled by the control register. A removing logic unit is used for removing, as indicated by the mode bit, a pixel from the plurality of input pixels upon a transition of one of the carry out signals of the base-n counter if the carry out signals have been enabled by the control register.

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First Claim