Software invalidation in a multiple level, multiple cache system
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United States of America Patent
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Dec 16, 1997
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N/A
app pub date -
Jun 7, 1995
filing date -
Dec 1, 1989
priority date (Note) -
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Abstract
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.
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