Parallel output buffers in memory circuits
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United States of America Patent
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Nov 18, 1997
Grant Date -
N/A
app pub date -
Dec 22, 1995
filing date -
Dec 22, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory circuit with programmable memory array organization and number of data output terminals, capable of connecting unused output buffers in parallel in organizations requiring fewer output terminals than the maximum possible. Parallel connection of output buffers improves output transient performance and employs otherwise dfsabled output buffers to reduce waste of silicon area.
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