Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory
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United States of America Patent
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Oct 21, 1997
Grant Date -
N/A
app pub date -
Nov 18, 1992
filing date -
Mar 15, 1985
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Abstract
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
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