Parity bit emulator with write parity bit checking
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United States of America Patent
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-
Sep 30, 1997
Grant Date -
N/A
app pub date -
May 19, 1995
filing date -
May 19, 1995
priority date (Note) -
Expired
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Abstract
A computer system includes a parity bit emulator circuit which generates a parity bit to be associated with a data byte output by a signal in-line memory module (SIMM) to a CPU. Each parity bit emulator monitors four consecutive write cycles to determine whether the system parity is even or odd, and thereafter monitors each write cycle to determine if a data transfer error has occurred during a write from the CPU to the SIMM. A state machine circuit provides appropriate timing for write and read cycle memory access protocols.
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