Method of fabricating DRAM cell with self-aligned contact
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United States of America Patent
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Sep 30, 1997
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app pub date -
May 29, 1996
filing date -
May 31, 1995
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Abstract
A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitance. The new structure uses a self-aligned contact where the contact can overlap the gate region in the layout.
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