Method for inspecting semiconductor devices on a wafer

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5654632
SERIAL NO

08689006

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method is disclosed, which sequentially inspects a plurality of semiconductor devices formed on a semiconductor wafer. This method executes a full inspection analysis on the individual devices on the wafer. The full inspection is carried out based on predetermined inspection criteria to determine whether or not the inspected devices are defective or properly functional. The number of devices determined as good ones during the full inspection analysis is sequentially counted, whereas the counted number is reset to zero whenever any device is determined to be defective during the full inspection routine. A simplified inspection analysis is executed on a predetermined number of devices when the counted number reaches a predetermined value. The simplified inspection is carried out against some of all the predetermined inspection criteria to determine whether or not the inspected devices are defects.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITED1-1 KAMIKODANAKA 4-CHOME NAKAHARA-KU KAWASAKI-SHI KANAGAWA 211-8588

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ohno, Yasukazu Kasugai, JP 7 92

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation