Processor having multiple instruction registers
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United States of America Patent
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-
Jul 15, 1997
Grant Date -
N/A
app pub date -
Nov 23, 1994
filing date -
Dec 28, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A program is stored alternately in the memories 1A and 1B one word at a time. One execution circuit 5 is induced to select and execute the outputs of instruction decoders 4A and 4B alternately. After the execution circuit 5 holds the output of the instruction decoder 4A (4B), the instruction decoder 4A (4B) is induced to decode the output of the instruction register 3A (3B), a program counter 2A (2B) is induced to update the output and a instruction register 3A (3B) is induced to hold the output of the memory 1A (1B).
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