Boundary-scan testable system and method
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United States of America Patent
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Jul 1, 1997
Issued Date -
N/A
app pub date -
Jun 17, 1996
filing date -
Nov 29, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system (10) includes any number of Boundary-Scan integrated circuits (28), a common bus (14), and a Boundary-Scan master (22). The integrated circuits (28) include mode selection logic (58) that isolates pins (30, 32) from core logic (34) during Capture-DR, Update-DR, Run-Test/Idle, and Select-DR-Scan states (66, 88, 62, 64) when a system action instruction is active so that a system action may be asserted. During all other states, including a Shift-DR state (82), the pins (30, 32) remain coupled to the core logic (34). The Boundary-Scan master (22) includes an arbitration interface (112). The arbitration interface (112) requests control of the common bus (14) prior to the time when the integrated circuits (28) assert a system action. The Boundary-Scan master arbitration interface (112) then releases control of the common bus after system action by the integrated circuits (28) is completed.
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