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Abstract

A frequency detector is provided for carrier frequency synchronization in a digital receiver including a frequency control circuit having a voltage-controlled oscillator (VCO), a multiplier for the received signal and the VCO signal and a device to suppress double frequency signal terms of the product signal from the multiplier. The frequency detector includes cascades of complex bandpass filters and real or complex pre-equalizers, which include bandpass filters (BP) and pre-equalizers (VE) for the real part (x) and the imaginary part (y) of the product signal, and a logic circuit which has a combining device for the cascade output signals that forms a control signal (u.sub.f) for the voltage-controlled oscillator (VCO). The combining device squares or multiplies the cascade output signals to form resulting signals as a measure of power and subtracts the resulting signals from each other to produce the control signal. To improve carrier synchronization, especially in mobile radios, in particular with pattern jitter suppression in the case of offset modulation, at least two cascades, each composed of a pre-equalizer and a bandpass filter, have center frequencies having different absolute values situated in a frequency range of a single Nyquist edge of the power density spectrum of the demodulated received signal.

First Claim