PLL circuit of pulse swallow-type prescaler system

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United States of America Patent

PATENT NO 5640116
SERIAL NO

08481832

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Abstract

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A PLL circuit of the pulse swallow-type prescaler system prevents erroneous module count operations such as are caused by a delay in the module signal, without the need to use a device which operates at high speeds or a device of large power. In a synthesizer of the pulse swallow-type prescaler system, a PLL circuit has a PLL COUNTER circuit and a module pulse generating circuit and a prescaler circuit has a prescaler counter, an extender circuit and a module control circuit which outputs a module control signal MO, for controlling the module operation, upon sensing the logic state of the module pulse generating signal MK, which is output by the module pulse signal generating circuit in response to the output signal MD of the PLL counter circuit.

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Patent Owner(s)

  • FUJITSU LIMITED;FUJITSU VLSI LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kobayashi, Akira Kasugai, JP 188 2875
Saito, Shinji Kasugai, JP 330 5551

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