Sample/hold free most significant bit comparator using bisection comparators
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United States of America Patent
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May 20, 1997
Grant Date -
N/A
app pub date -
Mar 17, 1995
filing date -
Mar 17, 1995
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Abstract
This invention provides an analog to digital converter using bisection comparators to determine the Most Significant Bits of the input voltage. The bisection comparator is comprised of three inverting amplifiers and does not use an auto zero phase, which reduces the power dissipation in the bisection comparator significantly. The bisection comparator does not use a sample and hold circuit and no capacitors are required, which significantly reduces the size of the integrated circuit chip. The analog to digital converter uses a number of bisection comparators to determine the Most Significant Bits of the input voltage and fine analog to digital converters to determine the Least Significant Bits of the input voltage. The outputs of the bisection comparators are used to set the switches of the fine analog to digital converters.
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