Programmable electronic timer circuit
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United States of America Patent
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Apr 15, 1997
Grant Date -
N/A
app pub date -
Apr 10, 1995
filing date -
Apr 10, 1995
priority date (Note) -
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Abstract
A programmable timer circuit (18) includes a counter (22) that contains a plurality of sequentially arranged counter stages (22a, 22b). A toggle logic gate (25) is disposed between each sequential pair of counter stages to accept the output signal from the preceding stage and to issue an input signal to the succeeding counter stage. The logic state of the input signal is determined by the logic state of the preceding output signal and the logic state of a program stage signal from an associated program stage. The logic state of the program signal is determined by the state of a fuse (F) associated with the program stage. Selected fuses can be blown by a programming routine to adjust the time delay between the initiation signal and issuance of the output signal. This sets the counter stages at power-up to a predetermined logic state in which the output signal will be produced with a predetermined time delay when the initiation signal is applied to the integrated circuit. The program routine includes activating the counter stages that will be active at the desired count and issuing a programming signal to burn the fuse associated with the active counter stage.
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