Process for fabricating a CMOS structure with ESD protection
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United States of America Patent
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Apr 15, 1997
Grant Date -
N/A
app pub date -
Mar 11, 1996
filing date -
Mar 24, 1995
priority date (Note) -
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Abstract
A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions. The protective oxide layer is then subjected to a heat treatment, after which a siliciding process is carried out.
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