Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system
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United States of America Patent
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Mar 25, 1997
Issued Date -
N/A
app pub date -
Jun 6, 1995
filing date -
Jan 10, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
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