Apparatus and method for controlling the initiating of a synchronization protocol for synchronizing a plurality of processors in a multi-processor system
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United States of America Patent
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Mar 25, 1997
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N/A
app pub date -
Apr 4, 1995
filing date -
Jan 3, 1992
priority date (Note) -
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Abstract
A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.
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