Semiconductor integrated circuit device and method of manufacturing the same
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United States of America Patent
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Mar 11, 1997
Issued Date -
N/A
app pub date -
Apr 24, 1995
filing date -
Aug 5, 1992
priority date (Note) -
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Abstract
A plurality of memory cells have their sources and drains formed integrally with n.sup.+ -buried layers acting as first data lines in a semiconductor substrate. The n.sup.+ -buried layers are connected with second data lines through transfer MISFETs. These transfer MISFETs have their gates made of the same layer of polycrystalline silicon as that of the floating gates of memory cells are shunted at each predetermined number of bits by Al lines having a lower resistance than that of the polycrystalline silicon.
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