Clock recovering circuit for digital demodulator
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United States of America Patent
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Feb 11, 1997
Grant Date -
N/A
app pub date -
Jul 26, 1994
filing date -
Mar 10, 1993
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Abstract
A clock recovering circuit including a correlation detection circuit for sampling a signal of a plurality of sampling points fixed in advance for each unit data cycle and detecting correlations between each adjacent pair of the sampling points, a correlation judgment circuit for comparing the correlations detected by the correlation detection circuit, judging the pair of sampling points which maximize the correlation and another pair of sampling points providing the next largest correlation and producing a timing clock signal based on the sampling point which is a common sampling point with respect to the two pairs of sampling points providing the largest and the next largest correlation, and a phase shift circuit for shifting the phase of the signal so as to equalize the correlations of the two pairs of sampling points so that the timing clock signal which is produced by the common sampling points is always generated at a point at which an eye pattern of the signal opens most widely.
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