Constant delay logic circuits and methods
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United States of America Patent
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Feb 4, 1997
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app pub date -
Sep 13, 1994
filing date -
Aug 18, 1994
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Abstract
A partitioned constant delay logic network 208 has a number of constant delay logic elements. The delay of each logic element is held constant by applying a controlled bias voltage, V.sub.bias. The source of the controlled bias voltage is a phase locked loop 201 which has a voltage controlled oscillator 203 constructed out of an odd plurality of constant delay logic elements.
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