Static random access memory dynamic address decoder with non-overlap word-line enable
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United States of America Patent
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Jan 28, 1997
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N/A
app pub date -
Jun 23, 1995
filing date -
Jun 23, 1995
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Abstract
An address decoder having non-overlapping word line enable is disclosed having a dynamic logic gate-based decoding section. The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further includes a NOR logic having an output for coupling to a memory word line which is gated by the deadtime signal to disable the output while the transmission gate passes the decoder output to the latch. When the deadtime pulse transitions to a low state, the latch captures the decoder output signal and enables the output of the NOR gate.
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