High speed dual-slope analog-to-digital converter
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United States of America Patent
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Jan 7, 1997
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N/A
app pub date -
Apr 29, 1994
filing date -
Apr 29, 1994
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Abstract
A unified zero-reset phase is used in a dual-slope analog-to-digital converter (ADC) to: (1) derive a correction voltage to cancel any error due to offset and/or residue voltages in the components of the ADC in the subsequent integration phase and the de-integration phase; (2) reset the output of the integrator in the ADC to zero quickly when there is a overflow condition due to excessive analog input signals. The combined function is accomplished by negative feedback from the output of the comparator to the input of the buffer. The negative feedback resets the integrator output to zero quickly under overflow condition. The correction voltage is stored in the integrating capacitor and a coupling capacitor to the integrating amplifier.
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