Low-capacitance, isotropically etched antifuse and method of manufacture therefor
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United States of America Patent
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Dec 24, 1996
Grant Date -
N/A
app pub date -
May 25, 1994
filing date -
May 25, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides for an integrated circuit antifuse structure having a first metal interconnection line, a programing layer over the first interconnection line, an etch stop layer over the programming layer, a sacrificial buffer layer over the etch stop layer, an insulating layer over the buffer layer, and a second metal interconnection line over the insulating layer. An aperture extends through the insulating layer and the buffer layer. The buffer layer has etching characteristics which are different from those of the insulating layer and the etch stop layer. This permits the aperture through the insulating layer to be formed with substantially vertical sides and through the buffer layer to be formed with substantially sloped sides. The second interconnection line extends into the aperture to form an antifuse structure with a low capacitance and a consistent programming voltage.
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