Process for manufacturing a stacked integrated circuit package
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United States of America Patent
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Dec 24, 1996
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N/A
app pub date -
Oct 18, 1994
filing date -
Jun 24, 1987
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Abstract
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
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