Manufacturing method or an exposing method for a semiconductor device or a semiconductor integrated circuit device and a mask used therefor

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United States of America Patent

PATENT NO 5578422
SERIAL NO

08443431

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATION2-24 TOYOSU 3-CHOME KOTO-KU TOKYO 135-0061

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mizuno, Fumio Tokorozawa, JP 47 920
Morita, Masayuki Fussa, JP 70 803
Moriuchi, Noboru Ohme, JP 16 388
Shirai, Seiichiro Hamura, JP 15 193

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