Synchronous DRAM tester
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United States of America Patent
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Oct 29, 1996
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N/A
app pub date -
Apr 28, 1995
filing date -
Apr 28, 1995
priority date (Note) -
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Abstract
A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.
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