Synchronous power down clock oscillator device
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United States of America Patent
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Oct 22, 1996
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N/A
app pub date -
Sep 22, 1995
filing date -
Sep 22, 1995
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Abstract
This invention provides a synchronous, power down oscillating device that provides only uniform pulses having no glitches at its output. The circuit is able to provide a synchronous output for two low power stand-by modes of a battery powered device. The circuit includes an oscillator that sends an oscillator signal to a synchronizing chain of D flip-flops. Input to the flip-flops is provided through an OR gate. The output of the flip-flops is logically ORed with the oscillator signal. The resultant output from the circuit is always a synchronized signal.
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