Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation
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United States of America Patent
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Oct 8, 1996
Issued Date -
N/A
app pub date -
Feb 24, 1994
filing date -
Apr 20, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A microprocessor having a buffer or memory capable of holding a plurality of instructions in advance of execution also functions to insert a special bus cycle amongst the instructions for outputting the internal information of the microprocessor to the outside in a predetermined operation mode at the time of each execution. The information inside of the microprocessor, which is to be outputted to the outside in the special bus cycle, is identified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In an emulation of the system using the instruction prefetch type microprocessor, as described above, what instruction has been executed can be easily known from the outside to effect an accurate emulation analysis and to facilitate the analysis of trace data thereby to improve debugging efficiency.
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