Method of making a three-dimensional integrated circuit
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United States of America Patent
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Oct 8, 1996
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N/A
app pub date -
Sep 22, 1995
filing date -
Sep 22, 1994
priority date (Note) -
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Abstract
A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then reduced in thickness from its opposite surface. The auxiliary layer with the devices thereon is then separated into individual chips which after having been found to be functioning are aligned and mounted in a side-by-side arrangement on said one surface of said first substrate. Electrical connection are formed between the devices of the mounted chips and the devices in the first substrate.
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