Apparatus and method for protecting data in a memory address range
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United States of America Patent
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Sep 24, 1996
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N/A
app pub date -
Jan 11, 1993
filing date -
Jan 11, 1993
priority date (Note) -
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Abstract
A data protection apparatus has chip select logic, a protection circuit and one or more memory devices. The chip select logic is designed so that when protected memory is addressed, more than one selection signal is generated. In this way, a protected memory area may encompass all, or a portion, of one or more memory devices. The additional selection signal is processed by a protection circuit which will interrupt the processor if protected memory is addressed during a write cycle in the absence of a request signal which the processor is programmed to generate just prior to its writing to a protected memory area.
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