Graphics processor enhancement unit
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United States of America Patent
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Sep 24, 1996
Grant Date -
N/A
app pub date -
Feb 2, 1994
filing date -
Feb 2, 1994
priority date (Note) -
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Abstract
A graphics processor enhancement system having a processor connected through data and lower address lines to two areas of random access memory (RAM). One area of RAM stores an image frame and the other area of RAM stores a copy of a background section of the image frame. The processor is connected through a read/write line and higher address lines to a programmable logic device (PLD), the output of which functions to enable one of the two areas of RAM. The system also stores a transparent memory map containing a copy of the object surrounded by transparent pixel values. The processor provides an animated display by modifying a portion of the image frame, such that an object stored therein is incremental moved across the image frame. The PLD enables the processor to read the copied background section, overlay this background section with the transparent memory map and write the resulting combination to the image frame over the old object stored therein. The resulting image frame includes the object at a new location.
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