Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements
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United States of America Patent
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Aug 27, 1996
Issued Date -
N/A
app pub date -
Sep 30, 1994
filing date -
Feb 3, 1992
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Expired
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Abstract
A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.
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