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Abstract

A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs. The delay element may be implemented as a shift register and the memory device may be implemented as at least one programmable read only memory (PROM) integrated circuit. A counter circuit determines the beginning of each fixed data cycle interval and the rate at which said fixed data cycles occur, which rate is between 500 kilobits (Kbs) and sixteen megabits per second (Mbs). The filter operates as a 319 tap FIR filter at a data input rate of 500 Kbs and as a 19 tap FIR filter at a data input rate of 16 Mbs.

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