Circuit and method of indicating data hold-time
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United States of America Patent
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Aug 20, 1996
Grant Date -
N/A
app pub date -
Jul 18, 1994
filing date -
Jul 18, 1994
priority date (Note) -
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Abstract
A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.
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