Method and apparatus for a single instruction operating multiple processors on a memory chip
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United States of America Patent
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Aug 13, 1996
Issued Date -
N/A
app pub date -
Apr 7, 1994
filing date -
Oct 18, 1990
priority date (Note) -
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Abstract
A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer is comprised of in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing a same operation function on each bit of the data in parallel to provide a result.
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