Importance

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Abstract

A memory device (10) is provided which includes a memory array (12), a multiplexer block (14) and a control block (16). The memory array (12) is operable to provide a plurality of memory array outputs (28.sub.1 . . . 28.sub.n) responsive to a memory address (MEMORY ADDRESS). Each memory array output (28.sub.1 . . . 28.sub.n) represents a data state of a memory cell. The multiplexer block (14) comprises at least one latch block (30.sub.1 . . . 30.sub.i, 32.sub.1 . . . 32.sub.j, 34.sub.1, 34.sub.2, and 36) arranged in at least one stage. The multiplexer block is coupled to the plurality of memory array outputs (28.sub.1 . . . 28.sub.n). The multiplexer block (14) is operable to provide a multiplexer block output (38) representing a data state of a desired memory cell corresponding to the memory address (MEMORY ADDRESS) responsive to a plurality of multiplexer control signals (44.sub.1 . . . 44.sub.m). Each latch block is operable to receive a plurality of input signals, operable to retain a plurality of data states and operable to provide an output signal. A control block (16) is coupled to the memory array (12) and to the multiplexer block (14). The control block (16) is operable to determine from the memory address (MEMORY ADDRESS) whether the data state of the desired memory cell is retained by a latch block in the multiplexer block (14) and operable to generate the plurality of multiplexer control signals (44.sub.1 . . . 44.sub.m).

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First Claim