Parallel testing of CPU cache and instruction units
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United States of America Patent
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Jul 23, 1996
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N/A
app pub date -
Jun 16, 1995
filing date -
Jun 16, 1995
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Abstract
A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal cache and causing that routine to be executed by the tested IU to test the previously untested portion of the internal cache while simultaneously testing any other IUs and circuitry on the CPU microprocessor. A system is disclosed for performing the method.
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