Pipelined read write operations in a high speed frame buffer system
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United States of America Patent
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Jul 23, 1996
Grant Date -
N/A
app pub date -
Oct 29, 1993
filing date -
Oct 29, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.
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