Drill coordinate optimization for multi-layer printed circuit board
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United States of America Patent
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Jun 25, 1996
Issued Date -
N/A
app pub date -
May 1, 1995
filing date -
Feb 28, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for optimizing drill coordinates in a multi-layer printed circuit board, to correct for interlayer shift during lamination. A set of test patterns, in the form of a cross formed by two orthogonal conductor lines, are defined at each corner of each layer in the same nominal location. Under ideal conditions, the test patterns of the layers in each corner are lined up one above the other, without any offset. A counter sinking tool is used to cut a conical bore in the location of the test patterns, so that every test pattern cross is interrupted in four places, generating a four segment pattern in each layer. A high resolution camera is placed above the countersunk bore to form a single image of the exposed segment edges of all the test patterns exposed by the bore. The image is analyzed to determine the amount of shift of each layer. If all patterns are perfectly concentric, all crosses are perfectly aligned. By measuring the shift of each pattern from the nominal position, the amount of shift in each layer is determined. The process is repeated for the test patterns at each corner of the board, and the resultant layer shift data is processed to optimize the drilling pattern for the board.
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