Low-capacitance, plugged antifuse and method of manufacture therefor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 28, 1996
Grant Date -
N/A
app pub date -
May 25, 1994
filing date -
May 25, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An antifuse structure in an integrated circuit is provided. The antifuse structure has a first metal interconnection line and a first insulating layer over the first metal interconnection line. The first insulating layer has a via exposing a top surface of the first metal interconnection line. In the first aperture a metal plug contacts the first metal interconnection layer and has a top surface substantially coplanar with a top surface of the first insulating layer. A metal pad contacts and covers the top surface of the metal plug. The metal pad should be formed by a viscous barrier metal, such as TiW, to smooth the surface of the metal plug. A second insulating layer, relatively thin with respect to said first insulating layer, covers the metal pad and has an aperture exposing a top surface of the metal pad. A programming layer deposited over the second insulating layer and into the aperture contacts the top surface of metal pad. A second metal interconnection line rests on the programming layer. In an alternative embodiment the locations of the second insulating layer and the programming layer are reversed.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully